Jarred (Jonghun) Shin

Education

• Kyungpook National University, Daegu, South Korea

  Expected Feb 2028

  B.S. in Electronics Engineering, Advanced Semiconductor Convergence major

Research Experience

• Programming a NAND flash string in TCAD, from FN tunneling to hot-carrier injection

  Sep 2026 – Present

  Team of six

  • Built a 7-gate SONOS NAND string in Sentaurus, got program, erase and ISPP working with FN tunneling, and am now reproducing a published hot-carrier programming scheme on it.
  • Simulated program, erase and ISPP on a 7-gate SONOS NAND string in Sentaurus TCAD (nonlocal tunneling, charge-trap layer traps).
  • Compared planar and cylindrical (gate-all-around) solutions of the same stack; the cylindrical cell showed about twice the threshold shift (+7.10 V vs +3.48 V at 20 V, 100 µs).
  • Reproducing the bilateral hot-carrier programming scheme of Kim et al. and tracking why injection into the trap layer does not yet appear.

  Sentaurus TCAD · SDE · SDevice · SVisual · Python · Linux

Projects

• How one grain boundary changes a capacitorless DRAM cell

  Sep 2026 – Present

  Team project, Semiconductor Device Design Lab course

  • In simulation, a single grain boundary in the poly-Si channel cut the sensing margin of a 1T-DRAM cell by 27%, close to the 25% reported in the literature.
  • Simulated a poly-Si capacitorless DRAM (1T-DRAM) cell in Sentaurus TCAD and varied the position and trap density of a grain boundary in the channel.
  • Wrote Python scripts to generate Workbench experiment tables (47 DC and 37 memory runs) and to export read currents from transient results.

  Sentaurus TCAD · Sentaurus Workbench · Python · Linux

• Designing an 8×8 SRAM from the cell up

  Sep 2026 – Present

  Team of six, semiconductor design club

  • A 64-bit 6T SRAM with precharge, row decoder, write drivers and sense amplifiers; all 64 cells pass write-then-read in simulation.
  • Designed a 6T SRAM cell and an 8×8 array with precharge, 3-to-8 row decoder, write drivers and latch-type sense amplifiers in Cadence Virtuoso.
  • Sized the cell by sweeping 507 width combinations in Spectre with scripted pass/fail checks for write, read disturb and read differential voltage.
  • Verified the full array in simulation (64 of 64 cells pass write-then-read); layout and tape-out are the next stage.

  Cadence Virtuoso · Spectre · Python · Linux

• A CMOS test chip, from layout to probe station

  Mar 2026 – Jun 2026

  Team of five, Integrated Circuit Process Lab course

  • Designed a 2 cm × 2 cm test chip with nine structure types, ran lithography and etch experiments in the cleanroom, and extracted contact resistance and threshold voltage from fabricated devices.
  • Laid out a 2 cm × 2 cm CMOS test chip in KLayout (TLM, NMOS/PMOS, inverter, NAND/NOR, three SR-latch variants) under λ = 5 µm design rules.
  • Ran a maskless-lithography dose test (optimum 50 mJ/cm² for 1 µm resist) and CF₄/O₂ RIE experiments in the cleanroom.
  • Measured fabricated devices on a probe station; extracted contact resistance by TLM (71.9 Ω n-type, 49.4 Ω p-type) and NMOS threshold voltage by the gm-max method (2.01 V).

  KLayout · Maskless lithography · RIE · Probe station · Keithley 2612B · Oscilloscope

• Edge UAV for real-time pothole detection

  Sep 2025 – Feb 2026

  Team of five · drone platform and camera input

  • A quadcopter that spots a pothole on its own, stops over it, and sends the photo, GPS position and a risk level to a web map.
  • Owned the drone side of a five-person project: flight platform, camera mounting and the image input feeding onboard detection.
  • Team trained YOLOv8 on 5,396 images (mAP 0.898 after relabelling) and deployed it on a Jetson Orin Nano with TensorRT (FP16).
  • Detection triggers a MAVLink BRAKE command to the Pixhawk; the event (image, GPS, altitude, risk level) is uploaded to a Flask-based web map.
  • Co-author of a paper submitted to JCCI 2026.

  Jetson Orin Nano · Pixhawk · MAVLink · YOLOv8 · TensorRT · OpenCV · Flask · Python

Activities & Leadership

• Tutor and buddy for international students

  Sep 2026 – Present

  Tutor (university programme) and buddy (School of Electronics Engineering)

  • Help international students at Kyungpook National University settle into classes and daily life, in Korean and English.

• Engineering kits for children, with POSCO Beyond

  Mar 2026 – Aug 2026

  Member, 19th cohort

  • Designed and built hands-on engineering kits and taught with them at community child centres in Korea and at an elementary school overseas.

Training

• SK hynix Semiconductor Curriculum, 5th cohort

  Sep 2026 – Present

  Self-nomination track

  • Selected for the self-nomination track of SK hynix's semiconductor education programme, covering memory devices, fabrication, packaging, reliability and metrology.

Publications

• S. Lee, J. Moon, J. Shin, C. Ahn, S. Lim, "Design of Real-Time Pothole Detection and Automated Control System for UAVs Based on Edge Computing and MAVLink," submitted to the 36th Joint Conference on Communications and Information (JCCI 2026).

Certifications

• OPIc English: Intermediate High (IH)May 2026
• Ultralight Vehicle Pilot Certificate, Class 4 (unmanned multicopter)

Skills

Device simulation

Sentaurus TCAD (SDE, SDevice, SVisual, Workbench)

Circuit design and layout

Cadence Virtuoso · Spectre · KLayout · PSpice

Process and measurement

Maskless lithography · RIE · Probe station · Source meter (Keithley 2612B) · Oscilloscope

Programming

Python · C++ · Linux

Embedded

Jetson Orin Nano · Pixhawk / MAVLink · OpenCV

Language

Korean (native) · English (OPIc IH)