A CMOS test chip, from layout to probe station

This was the project for the Integrated Circuit Process Lab course at Kyungpook National University: five of us designed a test chip, practised the process steps in the cleanroom, and measured real devices. With five people and one chip, everyone worked on every stage, and so did I.

It did not go to plan, which turned out to be the useful part.

The layout

We wanted a chip where a failure could be traced back to its cause. So the structures build on each other:

1. TLM patterns, to check that contacts to the diffusion are ohmic.
2. Single NMOS and PMOS in several width and length combinations.
3. Inverter, then NAND and NOR.
4. SR latch, in three versions: a basic one, a multi-finger one with the same total width, and an asymmetric one sized to favour reset.

If the inverter fails but the single transistors work, the problem is in the wiring, not the devices.

The process has one metal layer, so no wire can cross another. That shaped everything: where the power and signal pads go, and why the two NAND gates of each latch face each other to keep the feedback wires short. We used conservative dimensions (λ = 5 µm, so 10 µm minimum width and spacing) and repeated every structure several times, expecting some to be lost to defects.

Lithography: finding the dose

For a 1 µm resist layer we worked out the spin speed from the resist’s spin curve (4000 rpm) and ran a dose test from 30 to 100 mJ/cm² in 5 mJ/cm² steps on a 405 nm maskless aligner.

• Below 40 mJ/cm² the pattern did not open fully and resist was left behind.
• Above 55 mJ/cm² the exposed area spread and the pattern distorted.
• 50 mJ/cm² gave the sharpest edges.

With that dose lowered slightly to 45 mJ/cm², lines of 1.5, 2 and 3 µm resolved cleanly. The 1 µm lines did not. At that pitch the diffraction blur from each edge, roughly half a micron, overlaps with its neighbour and the gap is effectively overexposed.

Etching: a recipe that did not transfer

The day before the etch session the target changed to SnS₂ on a sapphire substrate. We borrowed a CF₄/O₂ recipe that had worked for SnS₂ on SiO₂ and lowered the RF power from 280 W to 100 W to protect the new substrate.

At 100 W almost nothing was etched. At 280 W the etch worked but 20 seconds was not enough to clear the film. Looking back, the cautious first run cost us the one extra attempt we needed, and we should have arrived with backup recipes prepared.

Measurement: not our chip

Our metal mask was drawn for negative resist. The process used positive resist. The metal pattern came out inverted and our chip could not be measured.

We measured spare devices made in the same run instead. That meant giving up the latch comparisons the layout was designed for, but the order of measurement stayed the same.

Contacts. Total resistance against contact spacing was linear for both types (R² above 0.99), which is what ohmic contacts look like. Contact resistance came out at 71.9 Ω for n-type and 49.4 Ω for p-type.

NMOS. The gate controlled the current over about three orders of magnitude. Threshold voltage by the gm-max method was 2.01 V. Current fell clearly as channel length increased, the most reliable trend in the data.

PMOS. No gate control at all. Under the microscope the n-well had spread until it overlapped the metal pads, shorting source and drain to the substrate. The transistor was behaving as a resistor.

Inverter. The output inverted, but with a swing of a few hundred millivolts instead of the full 5 V. With the PMOS broken, that was expected.

What I took from it

The mask polarity error was a one-line detail in a process sheet, and it cost us the experiment the whole layout was built for. I now check that kind of assumption with the people running the process before drawing anything.