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결정립계 하나가 커패시터리스 DRAM 셀에 미치는 영향
시뮬레이션에서 폴리실리콘 채널의 결정립계 하나가 1T-DRAM 셀의 센싱 마진을 27% 줄였고, 이는 문헌에 보고된 약 25%와 가깝습니다.
- 기간
- 2026.09 – 현재
- 역할
- Team project, Semiconductor Device Design Lab course
- 도구
- Sentaurus TCAD · Sentaurus Workbench · Python · Linux
- 상태
- 진행 중
- 결과
- 시뮬레이션에서 폴리실리콘 채널의 결정립계 하나가 1T-DRAM 셀의 센싱 마진을 27% 줄였고, 이는 문헌에 보고된 약 25%와 가깝습니다.
아래 상세 내용은 영어로만 제공됩니다.
A capacitorless DRAM cell (1T-DRAM) stores its bit as holes in the body of a single transistor, with no capacitor. If the channel is polycrystalline silicon, somewhere in it there is a grain boundary, and its traps are a place for those stored holes to disappear.
This is our team project in the Semiconductor Device Design Lab course at Kyungpook National University. We took a published poly-Si 1T-DRAM (Lee et al., IEEE Access, 2021) as the reference device and asked how much one grain boundary costs, and whether its position matters.
Method
The cell is built in Sentaurus. The grain boundary is an interface inside the channel with donor-like and acceptor-like trap distributions, and its position along the channel is a parameter. We look at two things:
- DC: the Id-Vg curve, to see how the boundary shifts the threshold.
- Memory operation: a transient that writes, holds and reads, giving the read current for a stored 1 and a stored 0. The difference is the sensing margin.
Sentaurus Workbench generates every combination of the parameters you give it, which quickly becomes hundreds of rows. Instead of clicking through that, we wrote Python scripts that produce only the rows we want: 47 for DC and 37 for memory.
Results so far
| Read 1 | Read 0 | Sensing margin | |
|---|---|---|---|
| No grain boundary | 11.06 | 3.76 | 7.30 µA/µm |
| One grain boundary | 7.37 | 2.07 | 5.30 µA/µm |
One boundary takes 27% off the sensing margin. The paper reports about 25% for the same comparison. Our absolute currents are lower than the paper’s, about three quarters of theirs, and our spacer material differs, so the match in the percentage may be partly luck.
Raising the trap density reduces the margin steadily. Up to a hold time of 10 µs we see no retention loss at all. Any effect of the boundary on retention must appear at millisecond hold times, and those runs are next.
A mistake worth keeping
Our export script picked the read current by matching a time stamp with a relative tolerance. For long hold times that tolerance was wider than the spacing between time points, so it picked the wrong point. For a day the data said that a grain boundary improves retention. It was the script. After switching to an absolute tolerance the numbers made sense again.
We also tested a split work-function gate, hoping it would soften the effect of the boundary. It raised the sensing margin overall but did not reduce the boundary’s share of the loss. It is a way to get more margin, not a way to cancel the grain boundary.
Next
Retention at 1 ms and 64 ms, to check the paper’s claim that the cell still holds for 64 ms with a grain boundary.