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셀부터 설계한 8×8 SRAM
프리차지, 로우 디코더, 라이트 드라이버, 센스 앰프를 갖춘 64비트 6T SRAM을 설계했고, 시뮬레이션에서 64개 셀 모두 쓰기 후 읽기를 통과했습니다.
- 기간
- 2026.09 – 현재
- 역할
- Team of six, semiconductor design club
- 도구
- Cadence Virtuoso · Spectre · Python · Linux
- 상태
- 진행 중
- 결과
- 프리차지, 로우 디코더, 라이트 드라이버, 센스 앰프를 갖춘 64비트 6T SRAM을 설계했고, 시뮬레이션에서 64개 셀 모두 쓰기 후 읽기를 통과했습니다.
아래 상세 내용은 영어로만 제공됩니다.
An SRAM cell is six transistors, and almost everything about it is a compromise between being easy to write and hard to disturb. In our semiconductor design club, six of us are taking one from a single cell to a working 8×8 array, with the aim of laying it out, fabricating it and measuring the chip.
The schematic design is finished. Layout comes next.
Sizing the cell
Two inverters hold the bit, and two access transistors connect it to the bit lines. Writing needs the access transistor to overpower the pull-up. Reading needs the pull-down to be stronger than the access transistor, or the read itself flips the cell. The widths of those three transistors decide both.
We started from the inverter. Sweeping the NMOS and PMOS widths between 1.6 and 3.0 µm showed how the switching point moves, and we aimed for the middle of the supply so the noise margin is the same on both sides.
For the cell we stopped doing it by hand. A script takes the netlist exported from Virtuoso, substitutes the three widths, runs Spectre in batch, and reads the node voltages back. Across 507 combinations it checks:
| Check | Criterion (VDD = 5 V) |
|---|---|
| Write succeeds | Stored node reaches within 0.5 V of the rail |
| Read does not disturb | Stored node moves less than 1 V during a read |
| Read is detectable | Bit-line difference of at least 0.2 V |
The first version of the testbench was too kind: no bit-line capacitance and a word line that switched in 1 ps. With a realistic 60 fF on the bit line and a 300 ps word-line edge, fewer sizes passed. We settled on 2.8 µm pull-down, 1.6 µm pull-up and 1.6 µm access.
Around the cell
- Precharge. Our first attempt pulled the bit lines up with a current source. It could not be switched off, so it kept feeding current during the read and fought the cell. Three PMOS devices on a precharge signal replaced it, one of them equalising the two bit lines so every read starts from the same point.
- Row decoder. A 3-to-8 decoder, each output a four-input NAND and an inverter, with an enable that keeps every word line low when it is off.
- Sense amplifier. A latch type. It waits for the cell to pull one bit line down, then resolves the difference to a full 0 or 5 V.
- Write driver. Pulls one bit line of the pair to ground according to the data.
When to sense
How long the sense amplifier waits after the word line rises matters. Too early and the difference is too small to trust on real silicon, where the two sides of the amplifier never match perfectly. Too late and the read is slow and the cell is exposed for longer.
| Wait after word line | Bit-line difference |
|---|---|
| 0 ns | 0.16 V |
| 0.1 ns | 0.67 V |
| 0.3 ns | 2.38 V |
| 0.5 ns | 3.86 V |
Every one of these read correctly in simulation, including 0 ns. We chose 0.3 ns anyway, because it leaves more than ten times the 0.2 V we consider the minimum, and simulation does not include transistor mismatch.
Result
With all blocks connected, every one of the 64 cells was written and read back correctly.
What simulation has not told us yet is area, wiring parasitics, or how the cell behaves across process corners on a real chip. That is what the layout and measurement stages are for.