TCAD로 구현한 NAND 플래시 프로그램 동작 (FN 터널링에서 HCI까지)

NAND flash is programmed by Fowler-Nordheim (FN) tunneling: put a high voltage on the word line and electrons tunnel into the charge-trap layer. It works, but it needs close to 20 V. Hot-carrier injection (HCI) is one proposed way to program at lower voltage.

In this project our team of six is building that behaviour up from nothing in Sentaurus TCAD. The target is the bilateral HCI scheme published by Kim et al. (“Enhanced programming efficiency in vertical NAND flash using self-boosting hot carrier injection”). We are reproducing it step by step rather than proposing something new, and the value has been in finding out how many things have to be right before a published figure can be reproduced at all.

The device

A string of seven gates over a poly-Si channel, with a SONOS stack:

Layer	Thickness
Inner oxide	25 nm
Poly-Si channel	8 nm
Tunnel oxide (SiO₂)	3 nm
Charge-trap layer	6 nm
Blocking oxide	9 nm

Gate length and spacing are 22 nm, as in the paper. The cell being programmed is the middle one, Gate 4.

Step 1: FN program and erase

Before trying HCI we needed a baseline that behaves like a flash cell. With nonlocal barrier tunneling and traps in the charge-trap layer, a 20 V, 100 µs pulse on Gate 4 moved the threshold voltage from 0.98 V to 4.47 V, and an erase pulse brought it back to 1.10 V.

Saving the structure at several times during the pulse showed where the charge goes. Electrons pile up in roughly the first 1.5 nm of the trap layer next to the tunnel oxide, and the average over the layer hides that.

Step 2: planar against cylindrical

Real V-NAND is a cylinder with the gate wrapped around the channel. Solving the same cross-section as a body of revolution, with the same voltages and timing, gave about twice the shift:

After 20 V, 100 µs	Planar	Cylindrical
ΔVth	+3.48 V	+7.10 V
Trapped electrons under Gate 4 (average)	1.2×10¹⁹ cm⁻³	2.6×10¹⁹ cm⁻³

At the tunnel-oxide edge the two are the same. The difference is in the middle of the trap layer, where the cylinder fills and the planar cell stays almost empty. That fits a wrapped gate concentrating the field at the inner surface, though we have not yet extracted the field profile to confirm it.

Step 3: ISPP

Production NAND does not use one big pulse. It steps the voltage up and checks after each step. We applied 16 to 20 V in 1 V steps, 10 µs each, to the same device, carrying the trapped charge from one pulse to the next:

Pulse	16 V	17 V	18 V	19 V	20 V
Vth (V)	1.12	1.36	1.71	2.20	2.79

The step in Vth grows with voltage but is still below the 1 V step in programming voltage, so the cell is not yet in the regime where one step in equals one step out.

Step 4: HCI, and what is not working yet

For the HCI schemes we matched the paper’s bias conditions and put FN, bilateral and unilateral HCI on the same time axis so they could be compared directly. At 14 V on the selected word line, all three gave almost the same small shift, between 0.055 and 0.080 V. There was no extra programming from hot carriers.

So the simulation runs, but it does not show the mechanism. We are going through the differences from the paper one at a time: our structure is planar where theirs is cylindrical, our tunnel oxide is a single SiO₂ layer where theirs is an oxide-nitride-oxide stack, and we have no select gates at the ends of the string. We also found that our program and read steps ramped the gate bias differently, which made an early threshold comparison meaningless until it was fixed.

Where it stands

FN program, erase and ISPP are working and understood. HCI is implemented but not yet reproduced. I would rather say that plainly than show a curve I cannot explain.